1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
|
#define UARTBASE 0x4000e400
#define UARTLOCATION 2
#define DTB_SRC 0x80000
#define DTB_DST 0x10000000
#define LINUX_ENTRY 0x8c000000
#define BC_REGISTER 0x80000000
.syntax unified
.thumb
.int 0x10020000 @ Initial SP value
.int reset + 1
#define UARTn_STATUS 0x0010
#define UARTn_STATUS_TXC 0x0020
#define UARTn_STATUS_TXBL 0x0040
#define UARTn_TXDATA 0x0034
@ load UART base address into \rx
.macro addruart, rx, tmp
ldr \rx, =(0x4000e400)
.endm
@ send char \rd with \rx holding the UART base address
.macro senduart, rd, rx
strb \rd, [\rx, #UARTn_TXDATA]
.endm
@ wait for the UART to become ready to take another char
.macro waituart, rd, rx
1001: ldr \rd, [\rx, #UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXBL
beq 1001b
.endm
@ wait for the fifo and shifter to become idle
.macro busyuart, rd, rx
1001: ldr \rd, [\rx, #UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXC
bne 1001b
.endm
/* printascii and printch are mostly copied from Linux v3.12, arch/arm/kernel/debug.S */
@ prints a zero-terminated string pointed to by r0
printascii:
addruart r3, r1
b 2f
1: /* send char in r1 */
waituart r2, r3
senduart r1, r3
teq r1, #'\n'
moveq r1, #'\r'
beq 1b
2: /* load next char from r0 */
teq r0, #0
ldrbne r1, [r0], #1
teqne r1, #0
bne 1b
busyuart r2, r3
bx lr
@ prints a single char contained in r0
printch:
addruart r3, r1
mov r1, r0
mov r0, #0
b 1b
.macro putc, val, cond=al
push {r0-r4}
mrs r4, APSR /* save cond flags */
mov r0, \val
bl\cond printch
msr APSR_nzcvq, r4 /* restore cond flags */
pop {r0-r4}
.endm
reset:
/* init external RAM, serial port, EBI and stuff */
adr r0, reginit
ldr r5, =(reginit_end)
1:
ldr r1, [r0]
ldr r2, [r0, #4]
str r2, [r1]
add r0, r0, #8
cmp r0, r5
blo 1b
/* init some BC registers */
adr r0, bcinit
ldr r5, =(bcinit_end)
1:
ldrh r1, [r0]
ldrh r2, [r0, #2]
add r1, r1, #BC_REGISTER
strh r2, [r1]
add r0, r0, #4
cmp r0, r5
blo 1b
/* give mux some time to enable the level shifter */
ldr r0, =0x4000
1: subs r0, r0, #1
bne 1b
/* First sign of life */
putc #'G'
/* if PB1 is pressed setup for SWO */
ldr r0, =(BC_REGISTER)
ldr r1, [r0, #8] @ BC_REGISTER->UIF_PB
tst r1, #1
putc #'e', ne
bne wait_boot_linux
putc #'E'
/* poll for CMU_STATUS_AUXHFRCORDY */
ldr r0, =(0x400c8000)
1:
ldr r1, [r0, 0x2c] @ CMU_STATUS
tst r1, #0x20
beq 1b
adr r0, swoinit
ldr r5, =(swoinit_end)
1:
ldmia r0!, {r1, r2, r3} /* load addr, mask, value */
teq r2, #0xffffffff
ldrne r4, [r1]
bicne r4, r2
orrne r3, r4
str r3, [r1]
cmp r0, r5
blo 1b
wait_boot_linux:
#ifdef CONFIG_WAIT_FOR_PB2
putc #'C'
/* only boot into Linux when PB2 is pressed */
ldr r0, =(BC_REGISTER)
1: ldr r1, [r0, #8] @ BC_REGISTER->UIF_PB
tst r1, #2
bne 1b
#else
putc #'c'
#endif
/* TFT setup */
/*wait for AEM button*/
ldr r0, =(BC_REGISTER)
putc #'\r'
putc #'\n'
wait:
putc #'P'
putc #'r'
putc #'e'
putc #'s'
putc #'s'
putc #' '
putc #'t'
putc #'h'
putc #'e'
putc #' '
putc #'A'
putc #'E'
putc #'M'
putc #' '
putc #'b'
putc #'u'
putc #'t'
putc #'t'
putc #'o'
putc #'n'
putc #'!'
putc #'\r'
putc #'\n'
/*pause*/
ldr r1, =0x700000
1:
ldrh r2, [r0, 0xe]
cmp r2, #1
beq aempress
subs r1, r1, #1
bne 1b
b wait
aempress:
putc #'O'
putc #'K'
putc #'\r'
putc #'\n'
adr r0, tft1
ldr r5, =(tft1_end)
1:
ldrh r1, [r0]
ldrh r2, [r0, #2]
add r1, r1, #BC_REGISTER
strh r2, [r1]
add r0, r0, 4
cmp r0, r5
blo 1b
/*pause*/
ldr r0, =0x75400
1: subs r0, r0, #1
bne 1b
adr r0, tft2
ldr r5, =(tft2_end)
1:
ldrh r1, [r0]
ldrh r2, [r0, #2]
add r1, r1, #BC_REGISTER
strh r2, [r1]
add r0, r0, 4
cmp r0, r5
blo 1b
adr r0, tft3
ldr r5, =(tft3_end)
1:
ldr r1, [r0]
ldr r2, [r0, #4]
str r2, [r1]
add r0, r0, #8
cmp r0, r5
blo 1b
adr r0, tft4
ldr r5, =(tft4_end)
spi:
ldr r1, [r0]
ldr r2, [r0, #4]
/*start with a pause*/
ldr r3, =0x20000
1: subs r3, r3, #1
bne 1b
/*clear port D of GPIO to enable chip select*/
ldr r3, =0x40006080
ldr r4, =0x8
str r4, [r3]
/*select register*/
ldr r3, =0x4000C400
ldr r3, [r3]
bic r3, r3, #0x200000
ldr r4, =0x4000C400
str r3, [r4]
/*write register on Tx*/
str r1, [r4, #0x34]
/*check that transmit buffer is empty*/
bl checkt
/*read data from Rx*/
ldr r3, [r4, #0x1c]
/*check that read buffer is empty*/
bl checkr
/*write data*/
ldr r3, [r4]
orr r3, r3, #0x200000
str r3, [r4]
/*write data high on Tx*/
lsr r3, r2, #8
str r3, [r4, #0x34]
bl checkt
/*read data from Rx*/
ldr r3, [r4, #0x1c]
bl checkr
/*write data low on Tx*/
mov r3, r2
uxtb r3, r3
str r3, [r4, #0x34]
bl checkt
/*read data from Rx*/
ldr r3, [r4, #0x1c]
bl checkr
/*set port D of GPIO to enable chip select*/
ldr r3, =0x4000607C
ldr r4, =0x8
str r4, [r3]
add r0, r0, #8
cmp r0, r5
blo spi
adr r0, tft5
ldr r5, =(tft5_end)
1:
ldr r1, [r0]
ldr r2, [r0, #4]
str r2, [r1]
add r0, r0, #8
cmp r0, r5
blo 1b
/*clear display*/
ldr r0, =0x883da000
ldr r1, =0x0000
ldr r2, =0x12C00
1:
strh r1, [r0]
add r0, r0, #2
subs r2, r2, #1
bne 1b
boot_linux:
putc #'k'
putc #'\r'
putc #'\n'
/* Copy oftree to RAM */
ldr r0, =(DTB_DST)
ldr r1, =(DTB_SRC)
ldr r2, [r1, #4]
rev r2, r2
bl memcpy
putc #'o'
putc #'\r'
putc #'\n'
/* boot Linux */
mov r0, #0
ldr r1, =#0xf11
ldr r2, =(DTB_DST)
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
ldr r7, =(LINUX_ENTRY + 1)
bx r7
memcpy:
@ copies r2 bytes from r1 to r0 with r2 > 0
ldrb r3, [r1], #1
strb r3, [r0], #1
subs r2, r2, #1
bhi memcpy
bx lr
/*check that transmit buffer is empty*/
checkt:
ldr r3, [r4, #0x10]
tst r3, #0x40
beq checkt
bx lr
/*check that read buffer is empty*/
checkr:
ldr r3, [r4, #0x10]
tst r3, #0x80
beq checkr
bx lr
.ltorg
.align 3
.type reginit, %object
reginit:
.int 0x400c8020, 0x00000014 @ CMU_OSCENCMD = HFXOEN | AUXHFRCOEN
.int 0x400c8008, 0x00000100 @ CMU_HFPERCLKDIV, reset default
.int 0x43900814, 0x00000001 @ CMU_HFCORECLKEN0 |= EBI via bitband
.int 0x439008b4, 0x00000001 @ CMU_HFPERCLKEN0 |= GPIO via bitband
.int 0x43900890, 0x00000001 @ CMU_HFPERCLKEN0 |= UART1 via bitband
/* pinmuxing */
/* A0: EBI_AD09
* A1: EBI_AD10
* A2: EBI_AD11
* A3: EBI_AD12
* A4: EBI_AD13
* A5: EBI_AD14
* A6: EBI_AD15
* A15: EBI_AD08
*/
.int 0x40006014, 0x0000807f @ GPIO_PA_DOUTCLR
.int 0x40006004, 0x04444444 @ GPIO_PA_MODEL
.int 0x40006008, 0x40000000 @ GPIO_PA_MODEH
/* B0: EBI_A16
* B1: EBI_A17
* B2: EBI_A18
* B3: EBI_A19
* B4: EBI_A20
* B5: EBI_A21
* B6: EBI_A22
* B9: UART1_TX#2
* B10: UART1_RX#2
* B15: MCU_EBI_CONNECT, output, 0
*/
.int 0x40006038, 0x0000807f @ GPIO_PB_DOUTCLR
.int 0x40006034, 0x00000200 @ GPIO_PB_DOUTSET; set UART_TX to avoid false start
.int 0x40006028, 0x04444444 @ GPIO_PB_MODEL
.int 0x4000602c, 0x40000140 @ GPIO_PB_MODEH
/* C11: EBI_ALE
*/
.int 0x4000605c, 0x00000800 @ GPIO_PC_DOUTCLR
.int 0x40006050, 0x00004000 @ GPIO_PC_MODEH
/* D0: USART1_TX#1 -> Ethernet (KSZ8851SNL)
* D1: USART1_RX#1
* D2: USART1_CLK#1
* D3: USART1_CS#1
* D9: EBI_CS0
* D10: EBI_CS1
* D11: EBI_CS2
* D12: EBI_CS3
* D13: #MCU_SPI_CONNECT, output, 1
* D14: I2C0_SDA#3
* D15: I2C0_SCL#3
*/
.int 0x4000607c, 0x0000fe08 @ GPIO_PD_DOUTSET
.int 0x40006080, 0x00000007 @ GPIO_PD_DOUTCLR
.int 0x40006070, 0x00004414 @ GPIO_PD_MODEL
.int 0x40006074, 0x88444440 @ GPIO_PD_MODEH
/* E0: irq line from Board controller
* E4: USART0_CS#1 -> Micro SD
* E5: USART0_CLK#1
* E6: USART0_RX#1
* E7: USART0_TX#1
* E8: EBI_AD00
* E9: EBI_AD01
* E10: EBI_AD02
* E11: EBI_AD03
* E12: EBI_AD04
* E13: EBI_AD05
* E14: EBI_AD06
* E15: EBI_AD07
*/
.int 0x400060a0, 0x00000011 @ GPIO_PE_DOUTSET
.int 0x400060a4, 0x0000ffe0 @ GPIO_PE_DOUTCLR
.int 0x40006094, 0x41440002 @ GPIO_PE_MODEL
.int 0x40006098, 0x44444444 @ GPIO_PE_MODEH
/* F6: EBI_BL0
* F7: EBI_BL1
* F8: EBI_WEn
* F9: EBI_REn
*/
.int 0x400060c8, 0x000003c0 @ GPIO_PF_DOUTCLR
.int 0x400060b8, 0x44000000 @ GPIO_PF_MODEL
.int 0x400060bc, 0x00000044 @ GPIO_PF_MODEH
.int 0x40006100, 0x00000004 @ GPIO_EXTIPSELL: select port E for irq 0
.int 0x4000610c, 0x00000001 @ GPIO_EXTIFALL: trigger for falling FPGA irq line
.int 0x4000611c, 0x0000ffff @ GPIO_IFC: clear all irqs
.int 0x40006110, 0x00000001 @ GPIO_IEN: enable irq 0
/* EBI */
.int 0x40008000, 0x4f00d051 @ EBI_CTRL, enable ITS, mode0=mode2=mode3=D16A16ALE, bl0-3, noidle[023]
/* EBI PSRAM */
.int 0x40008028, 0x10000000 @ EBI_ADDRTIMING2; HALFALE
.int 0x4000802c, 0x20000400 @ EBI_RDTIMING2; Prefetch, StrobeCycles = 4, HoldCycles = SetupCycles = 0
.int 0x40008030, 0x00000200 @ EBI_WRTIMING2; StrobeCycles = 2, HoldCycles = SetupCycles = 0
.int 0x40008034, 0x00000008 @ EBI_POLARITY2, ARDY_, ALE, WE_, RE_, CS_, BL_
/* Board Control FPGA */
.int 0x40008004, 0x10000303 @ EBI_ADDRTIMING; HALFALE, HoldCycles = SetupCycles = 3
.int 0x40008008, 0x00030703 @ EBI_RDTIMING; StrobeCycles = 7, HoldCycles = SetupCycles = 3
.int 0x4000800c, 0x00030703 @ EBI_WRTIMING; StrobeCycles = 7, HoldCycles = SetupCycles = 3
.int 0x40008010, 0x00000008 @ EBI_POLARITY, ARDY_, ALE, WE_, RE_, CS_, BL_
/* external NOR flash */
.int 0x40008038, 0x10000000 @ EBI_ADDRTIMING3; HALFALE, HoldCycles = SetupCycles = 0
#define PRE
#ifdef PRE
.int 0x4000803c, 0x00000700 @ EBI_RDTIMING3; StrobeCycles = 7, HoldCycles = SetupCycles = 0
.int 0x40008040, 0x00000200 @ EBI_WRTIMING3; StrobeCycles = 2, HoldCycles = SetupCycles =0
#else
/* reference: kits/common/bsp/bsp_dk_3201.c: 5 strobe cycles, hold=setup=0 */
.int 0x4000803c, 0x00000700 @ EBI_RDTIMING3; StrobeCycles = 7, HoldCycles = SetupCycles = 0
.int 0x40008040, 0x00000700 @ EBI_WRTIMING3; StrobeCycles = 7, HoldCycles = SetupCycles =0
#endif
.int 0x40008044, 0x00000008 @ EBI_POLARITY3, ARDY_, ALE, WE_, RE_, CS_, BL_
.int 0x40008014, 0x105e00bb @ EBI_ROUTE, location=1
.int 0x40008000, 0x4f00dd51 @ EBI_CTRL, enable ITS, mode0=mode2=mode3=D16A16ALE, bl0-3, noidle[023], bank[023]en
.int UARTBASE + 0x00, 0x00000000 @ UART1_CTRL
.int UARTBASE + 0x04, 0x00001005 @ UART1_FRAME
.int UARTBASE + 0x14, 0x00001900 @ UART1_CLKDIV
.int UARTBASE + 0x0c, 0x00000c04 @ UART1_CMD
.int UARTBASE + 0x54, 0x00000003 + (UARTLOCATION << 8) @ UART1_ROUTE
.int 0x400c8024, 0x00000002 @ CMU_CMD = HFCLKSEL_HFXO
reginit_end:
.size reginit, . - reginit
.align 3
.type bcinit, %object
bcinit:
.short 0x0018, 0x1701 @ enable UART mux, I2C, ETH and spi
.short 0x0014, 0x0001 @ /
.short 0x001a, 0x0001 @ ETH
.short 0x0042, 0x0010 @ workaround bug in BC's irq detection
.short 0x0040, 0x0010
bcinit_end:
.size bcinit, . - bcinit
.align 3
.type swoinit, %object
swoinit:
.int 0x40006120, 0x00000304, 0x00000004 @ GPIO_ROUTE: SWOPEN + LOCATION = 0
.int 0x400060b8, 0x00000f00, 0x00000400 @ configure F2 as pushpull output
.int 0xe000edf0, 0x00000001, 0x00000001 @ CoreDebug->DHCSR |= 1
.int 0xe000edfc, 0x01000000, 0x01000000 @ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk
.int 0xe0001000, 0xffffffff, 0x400113ff @ Enable PC and IRQ sampling output
.int 0xe0040010, 0xffffffff, 0x0000000f @ Set TPIU prescaler to 16.
.int 0xe00400f0, 0xffffffff, 0x00000002 @ Set protocol to NRZ
.int 0xe0000fb0, 0xffffffff, 0xc5acce55 @ Unlock ITM
.int 0xe0000e80, 0xffffffff, 0x00010009 @ output data
swoinit_end:
.size swoinit, . - swoinit
.align 3
.type tft1, %object
tft1:
.short 0x001a, 0x0002 @ Enable SPI to SSD2119
.short 0x0018, 0x1701 @ enable UART mux, ETH and spi
.short 0x0016, 0x0001 @ BSP_DisplayControl(BSP_Display_EBI)
.short 0x0012, 0x0002 @ BSP_DisplayControl(BSP_Display_ResetAssert)
tft1_end:
.size tft1, . - tft1
.align 3
.type tft2, %object
tft2:
.short 0x0012, 0x0006 @ BSP_DisplayControl(BSP_Display_ModeGeneric)
.short 0x0012, 0x0007 @ BSP_DisplayControl(BSP_Display_PowerEnable)
.short 0x0012, 0x0005 @ BSP_DisplayControl(BSP_Display_ResetRelease)
.short 0x0012, 0x0005 @ BSP_DisplayControl(BSP_Display_ResetRelease)
tft2_end:
.size tft2, . - tft2
.align 3
.type tft3, %object
tft3:
.int 0x40006014, 0x00008f7f @ GPIO_PA_DOUTCLR; EBI AD8..11 set dataout to 1
.int 0x40006008, 0x40004444 @ GPIO_PA_MODEH; EBI AD8..11 set mode=pushpull
/*CMU clock*/
.int 0x43900120, 0x00000001 @ CMU_ClockEnable(cmuClock_HFPER, true)
.int 0x43900884, 0x00000001 @ CMU_ClockEnable(cmuClock_USART1, true)
.int 0x439008B4, 0x00000001 @ CMU_ClockEnable(cmuClock_GPIO, true)
/*GPIO_PinModeSet(gpioPortD)*/
.int 0x40006080, 0x00000007 @ GPIO_PD_DOUTCLR, ETH_SPI_{TX, RX, CLK}
.int 0x4000607c, 0x0000fe08 @ GPIO_PD_DOUTSET, EBI CS0-3, spiconnect set dataout to 1; ETH_SPI_#CS (D3)
.int 0x40006070, 0x00004414 @ GPIO_PD_MODEL; ETH_SPI_
/*USART_Reset(USART1)*/
.int 0x4000C40C, 0x00000eaa @ USART1->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX | USART_CMD_CLEARRX
.int 0x4000C400, 0x00000000 @ USART1->CTRL = _USART_CTRL_RESETVALUE
.int 0x4000C404, 0x00001005 @ USART1->FRAME = _USART_FRAME_RESETVALUE
.int 0x4000C408, 0x00000000 @ USART1->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE
.int 0x4000C414, 0x00000000 @ USART1->CLKDIV = _USART_CLKDIV_RESETVALUE
.int 0x4000C44C, 0x00000000 @ USART1->IEN = _USART_IEN_RESETVALUE
.int 0x4000C448, 0x00001ff9 @ USART1->IFC = _USART_IFC_MASK
.int 0x4000C454, 0x00000000 @ USART1->ROUTE = _USART_ROUTE_RESETVALUE;
.int 0x4000C458, 0x00000000 @ USART1->INPUT = _USART_INPUT_RESETVALUE;
.int 0x4000C45C, 0x00000000 @ USART1->I2SCTRL = _USART_I2SCTRL_RESETVALUE
/*USART_InitSync(USART1, &inittft)*/
.int 0x4000C400, 0x00000701 @ USART1->CTRL |= (USART_CTRL_SYNC) | ((uint32_t)init->clockMode) | (init->msbf ? USART_CTRL_MSBF : 0)
.int 0x4000C404, 0x00001006 @ USART1->FRAME = ((uint32_t)(init->databits)) | (USART_FRAME_STOPBITS_DEFAULT) | (USART_FRAME_PARITY_DEFAULT)
.int 0x4000C414, 0x00001700 @ USART_BaudrateSyncSet(USART1, init->refFreq, init->baudrate)
.int 0x4000C40C, 0x00000015 @ USART1->CMD = USART_CMD_MASTEREN; USART1->CMD = (uint32_t)(init->enable)
.int 0x4000C454, 0x0000010b @ USART1->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | USART_ROUTE_LOCATION_LOC1
tft3_end:
.size tft3, . - tft3
.align 3
.type tft4, %object
tft4:
.int 0x00000028, 0x00000006 @ DMD_SSD2119_VCOM_OTP_1
.int 0x00000007, 0x00000023 @ DMD_SSD2119_DISPLAY_CONTROL
.int 0x00000010, 0x00000000 @ DMD_SSD2119_SLEEP_MODE_1
.int 0x00000007, 0x00000033 @ DMD_SSD2119_DISPLAY_CONTROL
.int 0x00000011, 0x00006730 @ DMD_SSD2119_ENTRY_MODE
.int 0x00000001, 0x000030ef @ DMD_SSD2119_DRIVER_OUTPUT_CONTROL
.int 0x00000002, 0x00000600 @ DMD_SSD2119_LCD_AC_CONTROL
.int 0x00000022, 0x000000ff @ DMD_SSD2119_ACCESS_DATA
tft4_end:
.size tft4, . - tft4
.align 3
.type tft5, %object
tft5:
/*Configure EBI TFT direct drive*/
.int 0x40008064, 0x003da000 @ EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset)
.int 0x4000806C, 0x00EF013F @ EBI_TFTSizeSet(ebiTFTInit->hsize, ebiTFTInit->vsize)
.int 0x40008070, 0x00780101 @ EBI_TFTHPorchSet(ebiTFTInit->hPorchFront, ebiTFTInit->hPorchBack, ebiTFTInit->hPulseWidth)
.int 0x40008074, 0x00100101 @ EBI_TFTVPorchSet(ebiTFTInit->vPorchFront, ebiTFTInit->vPorchBack, ebiTFTInit->vPulseWidth)
.int 0x40008078, 0x00000008 @ EBI_TFTTimingSet(ebiTFTInit->dclkPeriod, ebiTFTInit->startPosition, ebiTFTInit->setupCycles, ebiTFTInit->holdCycles)
.int 0x42100F80, 0x00000000 @ EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity)
.int 0x42100F84, 0x00000001 @ EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity)
.int 0x42100F88, 0x00000000 @ EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity)
.int 0x42100F90, 0x00000000 @ EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity)
.int 0x42100F8C, 0x00000000 @ EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity)
.int 0x4000805C, 0x00210002 @ EBI->TFTCTRL = ctrl modified
.int 0x40008014, 0x115e00bf @ EBI->ROUTE |= (EBI_ROUTE_TFTPEN)
.int 0x40008068, 0x00000000 @ EBI_TFTHStrideSet((V_WIDTH - D_WIDTH) * 2)
tft5_end:
.size tft5, . - tft5
|
